Computer Organization PrinciplesComputer Organization Principles

What will you learn from this article?What will you learn from this article?

After completing this chapter, you will gain:After completing this chapter, you will gain:

• System perspective: Understand how CPU, memory, and I/O work together — no longer just an isolated hardware enthusiastSystem perspective: Understand how CPU, memory, and I/O work together — no longer just an isolated hardware enthusiast
• Hardware terminology: Master hardcore concepts like instruction cycles, pipelines, CPI, and cache hit ratesHardware terminology: Master hardcore concepts like instruction cycles, pipelines, CPI, and cache hit rates
• Performance thinking: Understand bottlenecks and optimization approaches in computer organizationPerformance thinking: Understand bottlenecks and optimization approaches in computer organization
• Foundation for further learning: Build a professional foundation for operating systems, computer architecture, and embedded developmentFoundation for further learning: Build a professional foundation for operating systems, computer architecture, and embedded development

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0. Big Picture: Computer Hardware System0. Big Picture: Computer Hardware System

In the previous chapter "From Transistors to CPU," we understood how the CPU works internally — from fetch, decode, execute to write-back. But the CPU itself is just an execution unit. To make a computer truly "usable," a series of peripheral components must work together.In the previous chapter "From Transistors to CPU," we understood how the CPU works internally — from fetch, decode, execute to write-back. But the CPU itself is just an execution unit. To make a computer truly "usable," a series of peripheral components must work together.

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1. Von Neumann Architecture: The Foundation of Modern Computers1. Von Neumann Architecture: The Foundation of Modern Computers

1.1 The Stored-Program Principle1.1 The Stored-Program Principle

In 1945, mathematician John von Neumann proposed the groundbreaking stored-program architecture concept. This idea laid the foundation for modern computers.In 1945, mathematician John von Neumann proposed the groundbreaking stored-program architecture concept. This idea laid the foundation for modern computers.

This means:This means:

• Early computers: Programs were implemented through fixed wiring; changing a program required re-soldering circuitsEarly computers: Programs were implemented through fixed wiring; changing a program required re-soldering circuits
• Von Neumann architecture: Programs are stored in memory; changing a program only requires modifying the memory contentsVon Neumann architecture: Programs are stored in memory; changing a program only requires modifying the memory contents

1.2 Five Major Components1.2 Five Major Components

The Von Neumann architecture divides a computer into five core components:The Von Neumann architecture divides a computer into five core components:

1.3 Data Path1.3 Data Path

The Data Path is the route through which data flows between functional components. Inside the CPU, the data path connects:The Data Path is the route through which data flows between functional components. Inside the CPU, the data path connects:

• Register fileRegister file
• Arithmetic Logic Unit (ALU)Arithmetic Logic Unit (ALU)
• Memory Data Register (MDR)Memory Data Register (MDR)

The width of the data path (how many bits can be transferred at once) directly affects computer performance.The width of the data path (how many bits can be transferred at once) directly affects computer performance.

1.4 The Von Neumann Bottleneck1.4 The Von Neumann Bottleneck

The Von Neumann architecture has a famous performance bottleneck:The Von Neumann architecture has a famous performance bottleneck:

> The data transfer speed between CPU and memory is far lower than the CPU's processing speed.> The data transfer speed between CPU and memory is far lower than the CPU's processing speed.

This causes the CPU to frequently be in an idle "waiting for data" state. Many optimization techniques in modern computers revolve around this problem:This causes the CPU to frequently be in an idle "waiting for data" state. Many optimization techniques in modern computers revolve around this problem:

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2. Instruction Set Architecture: The Interface Between CPU and Software2. Instruction Set Architecture: The Interface Between CPU and Software

In the previous section, we learned the core idea of the Von Neumann architecture: programs are stored in memory just like data. But this raises a key question — what does a "program" stored in memory actually look like? How does the CPU understand it?In the previous section, we learned the core idea of the Von Neumann architecture: programs are stored in memory just like data. But this raises a key question — what does a "program" stored in memory actually look like? How does the CPU understand it?

The answer is the Instruction Set Architecture (ISA). If the CPU is a service, then the instruction set is its API documentation — it defines all the commands the CPU can understand, the format of each command, and the data range each command can operate on. Every line of code you write is ultimately translated by the compiler into a sequence of calls to this "API."The answer is the Instruction Set Architecture (ISA). If the CPU is a service, then the instruction set is its API documentation — it defines all the commands the CPU can understand, the format of each command, and the data range each command can operate on. Every line of code you write is ultimately translated by the compiler into a sequence of calls to this "API."

2.1 From Code to Instructions: Instruction Encoding and Execution2.1 From Code to Instructions: Instruction Encoding and Execution

First, let's establish a holistic understanding: the code you write in an editor and what the CPU actually executes are separated by several layers of translation.First, let's establish a holistic understanding: the code you write in an editor and what the CPU actually executes are separated by several layers of translation.

This translation chain is key to understanding instruction sets:This translation chain is key to understanding instruction sets:

2.2 Instruction Formats2.2 Instruction Formats

Now that we know code gets translated into instructions, the next question is: what is the internal structure of an instruction?Now that we know code gets translated into instructions, the next question is: what is the internal structure of an instruction?

Each machine instruction is essentially a string of binary digits, but it has a strict internal format. The two most core parts are:Each machine instruction is essentially a string of binary digits, but it has a strict internal format. The two most core parts are:

• Opcode: Tells the CPU "what to do" — add? jump? or read memory?Opcode: Tells the CPU "what to do" — add? jump? or read memory?
• Operand: Tells the CPU "what to do it to" — which register? which memory address? what constant?Operand: Tells the CPU "what to do it to" — which register? which memory address? what constant?

Just as a sentence has a "verb + object" structure, an instruction has an "operation + target" structure:Just as a sentence has a "verb + object" structure, an instruction has an "operation + target" structure:

Instruction: ADD R3, R1, R2 ─── ────────── Opcode Operands (do addition) (R3 = R1 + R2)

Based on the number of operands, instruction formats range from simple to complex in four types:Based on the number of operands, instruction formats range from simple to complex in four types:

2.3 Addressing Modes2.3 Addressing Modes

An instruction tells the CPU to "do addition," but where are the two numbers for the addition? They might be written directly in the instruction, in a register, or at some memory address. Addressing modes are the rules that tell the CPU "where to find the operands."An instruction tells the CPU to "do addition," but where are the two numbers for the addition? They might be written directly in the instruction, in a register, or at some memory address. Addressing modes are the rules that tell the CPU "where to find the operands."

Using a real-life analogy of "finding someone":Using a real-life analogy of "finding someone":

2.4 The CPU's Capability List — Instruction Categories2.4 The CPU's Capability List — Instruction Categories

Now that we know instruction formats and addressing modes, the last question is: what exactly can the CPU do?Now that we know instruction formats and addressing modes, the last question is: what exactly can the CPU do?

All instructions can be grouped into six categories that cover everything a computer can do:All instructions can be grouped into six categories that cover everything a computer can do:

2.5 Two Design Philosophies: CISC vs RISC2.5 Two Design Philosophies: CISC vs RISC

There is a fundamental divide in instruction set design: should each instruction be as powerful as possible, or as simple as possible?There is a fundamental divide in instruction set design: should each instruction be as powerful as possible, or as simple as possible?

This divide created two camps that directly affect every device you use today:This divide created two camps that directly affect every device you use today:

An analogy to understand this:An analogy to understand this:

• CISC is like a Swiss Army knife: One tool integrates scissors, a bottle opener, a screwdriver... lots of functions but each one may not be the bestCISC is like a Swiss Army knife: One tool integrates scissors, a bottle opener, a screwdriver... lots of functions but each one may not be the best
• RISC is like a professional tool set: Each tool does only one thing, but does it fast and wellRISC is like a professional tool set: Each tool does only one thing, but does it fast and well

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> Summary: The instruction set is the bridge between software and hardware. Your code is translated by the compiler into instructions, which tell the CPU what to do and to whom through opcodes and operands. Addressing modes determine where data comes from. Different instruction set designs (CISC/RISC) determine the CPU's performance characteristics and applicable scenarios.> Summary: The instruction set is the bridge between software and hardware. Your code is translated by the compiler into instructions, which tell the CPU what to do and to whom through opcodes and operands. Addressing modes determine where data comes from. Different instruction set designs (CISC/RISC) determine the CPU's performance characteristics and applicable scenarios.

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> Now we know the "static structure" of instructions — what they look like and what types exist. The next question is: how does the CPU execute these instructions step by step internally? That's the control unit's job.> Now we know the "static structure" of instructions — what they look like and what types exist. The next question is: how does the CPU execute these instructions step by step internally? That's the control unit's job.

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3. Control Unit: The CPU's Control Logic3. Control Unit: The CPU's Control Logic

3.1 Components of the Control Unit3.1 Components of the Control Unit

The control unit is the "brain" of the CPU, responsible for coordinating all components to work according to instruction requirements:The control unit is the "brain" of the CPU, responsible for coordinating all components to work according to instruction requirements:

3.2 Instruction Cycle3.2 Instruction Cycle

The CPU executes an instruction through a complete instruction cycle, typically including:The CPU executes an instruction through a complete instruction cycle, typically including:

1. Fetch Cycle: Read instruction from memory into IRFetch Cycle: Read instruction from memory into IR
2. Decode Cycle: Parse the instruction's meaningDecode Cycle: Parse the instruction's meaning
3. Execute Cycle: Perform the operationExecute Cycle: Perform the operation
4. Memory Access Cycle: Access memory if neededMemory Access Cycle: Access memory if needed
5. Write-Back Cycle: Write the result back to a register or memoryWrite-Back Cycle: Write the result back to a register or memory

3.3 Micro-Operations3.3 Micro-Operations

Micro-operations are the most basic operations driven by control signals. For example, the "fetch" phase can be decomposed into the following micro-operations:Micro-operations are the most basic operations driven by control signals. For example, the "fetch" phase can be decomposed into the following micro-operations:

Beat	Micro-Operation	Control Signals
T1	PC → MAR	PCout, MARin
T2	MEM → MDR	MEMout, MDRin
T3	MDR → IR	MDRout, IRin
T4	PC + 1 → PC	PC+1, PCin

3.4 Hardwired vs. Microprogrammed Control3.4 Hardwired vs. Microprogrammed Control

Feature	Hardwired Control	Microprogrammed Control
Implementation	Combinational logic circuits	Microinstruction sequences (firmware)
Speed	Fast	Slightly slower
Design difficulty	Complex	Simpler
Flexibility	Poor (changes require circuit redesign)	Good (just modify the microprogram)
Typical applications	RISC processors	Early CISC processors

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4. Storage Hierarchy and Cache Principles4. Storage Hierarchy and Cache Principles

4.1 Storage Hierarchy Structure4.1 Storage Hierarchy Structure

A computer's storage devices form a pyramid structure:A computer's storage devices form a pyramid structure:

Level	Storage Type	Access Time	Typical Capacity	Location
Registers	SRAM	<1ns	A few KB	Inside CPU
L1 Cache	SRAM	~1ns	32-64KB	Near CPU core
L2 Cache	SRAM	~3-10ns	256KB-1MB	On CPU chip
L3 Cache	SRAM	~10-20ns	2-16MB	On CPU chip / shared
Main Memory (RAM)	DRAM	~50-100ns	8-64GB	On motherboard
SSD	Flash	~10-100μs	256GB-2TB	On motherboard
HDD	Magnetic disk	~5-10ms	1-10TB	Inside case

💡 Tips Praktis💡 Pro Tip

If CPU accessing L1 cache is like grabbing a piece of paper from your desk: - Accessing main memory → Taking the elevator to a convenience store downstairs to buy paper - Accessing SSD → Driving to another city to buy paper - Accessing HDD → Flying to another country to buy paper The speed difference can be millions of times!If CPU accessing L1 cache is like grabbing a piece of paper from your desk: - Accessing main memory → Taking the elevator to a convenience store downstairs to buy paper - Accessing SSD → Driving to another city to buy paper - Accessing HDD → Flying to another country to buy paper The speed difference can be millions of times!

4.2 Cache Principles4.2 Cache Principles

Cache is fast storage located between the CPU and main memory. Its core idea is based on two locality principles:Cache is fast storage located between the CPU and main memory. Its core idea is based on two locality principles:

💡 Tips Praktis💡 Pro Tip

- Temporal locality: If data was just accessed, it's likely to be accessed again soon - Spatial locality: If data was accessed, nearby data is likely to be accessed too- Temporal locality: If data was just accessed, it's likely to be accessed again soon - Spatial locality: If data was accessed, nearby data is likely to be accessed too

How Cache WorksHow Cache Works

1. Hit: The data the CPU needs is in the cache; read directlyHit: The data the CPU needs is in the cache; read directly
2. Miss: The data is not in the cache; must be loaded from main memoryMiss: The data is not in the cache; must be loaded from main memory
CODE 📋 Salin📋 Copy

Hit rate = Number of hits / Total number of accesses Average access time = Hit rate × Cache time + (1 - Hit rate) × Memory time

4.3 Cache Mapping Methods4.3 Cache Mapping Methods

Method	Principle	Advantage	Disadvantage
Direct-mapped	Each memory block can only go to one fixed location	Simple and fast	High conflict rate
Set-associative	Each memory block can go to N locations (N-way)	Balances speed and hit rate	More complex implementation
Fully associative	Any location	Lowest conflict rate	Hardest to implement (requires comparing all tags)

4.4 Virtual Memory4.4 Virtual Memory

Virtual memory is an important abstraction provided by the operating system:Virtual memory is an important abstraction provided by the operating system:

• Each process thinks it has a complete virtual address spaceEach process thinks it has a complete virtual address space
• The operating system translates virtual addresses to physical addressesThe operating system translates virtual addresses to physical addresses
• Infrequently used pages can be swapped out to disk (swap space)Infrequently used pages can be swapped out to disk (swap space)
💡 Tips Praktis💡 Pro Tip

Think of virtual memory as a hotel managing rooms: - You (the process) think the entire building is yours - In reality, the hotel (OS) only assigns you the rooms you currently need - Unused rooms get "swapped out" to storage (disk) - Needed rooms can be "swapped in" at any timeThink of virtual memory as a hotel managing rooms: - You (the process) think the entire building is yours - In reality, the hotel (OS) only assigns you the rooms you currently need - Unused rooms get "swapped out" to storage (disk) - Needed rooms can be "swapped in" at any time

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5. Bus and I/O Systems5. Bus and I/O Systems

5.1 System Bus5.1 System Bus

A Bus is the data channel connecting computer components:A Bus is the data channel connecting computer components:

Bus Type	Function	Direction	Typical Width
Address Bus	Transfers memory addresses	Unidirectional (CPU→Memory)	32-bit/64-bit
Data Bus	Transfers data	Bidirectional	32-bit/64-bit
Control Bus	Transfers control signals	Bidirectional	Multiple signal lines

5.2 Bus Arbitration5.2 Bus Arbitration

When multiple devices simultaneously request bus access, an arbitration mechanism determines who goes first:When multiple devices simultaneously request bus access, an arbitration mechanism determines who goes first:

Arbitration Method	Description
Centralized arbitration	A central arbiter makes the decision
Distributed arbitration	Devices negotiate among themselves

5.3 I/O Device Access Methods5.3 I/O Device Access Methods

Method	Principle	Advantage	Disadvantage
Programmed I/O (Polling)	CPU polls I/O status	Simple	Low CPU utilization
Interrupt-driven I/O	I/O device actively notifies CPU when done	CPU can work in parallel	Interrupt handling has overhead
DMA	I/O device accesses memory directly	CPU not involved at all	Requires a DMA controller

5.4 DMA Principles5.4 DMA Principles

DMA (Direct Memory Access) allows I/O devices to exchange data directly with memory:DMA (Direct Memory Access) allows I/O devices to exchange data directly with memory:

• Without DMA: The CPU participates in the entire data transfer process and can't do anything elseWithout DMA: The CPU participates in the entire data transfer process and can't do anything else
• With DMA: The CPU tells the DMA controller "transfer from where to where, how much," then goes to do other tasks. The DMA notifies the CPU when completeWith DMA: The CPU tells the DMA controller "transfer from where to where, how much," then goes to do other tasks. The DMA notifies the CPU when complete
💡 Tips Praktis💡 Pro Tip

This is like ordering food delivery: - Without DMA: You go to the supermarket yourself, buy groceries, go home, wash vegetables, and cook (involved in the entire process) - With DMA: You place an order by phone, and the delivery person brings it straight to your kitchen (someone else handles it; you just "receive the goods" at the end)This is like ordering food delivery: - Without DMA: You go to the supermarket yourself, buy groceries, go home, wash vegetables, and cook (involved in the entire process) - With DMA: You place an order by phone, and the delivery person brings it straight to your kitchen (someone else handles it; you just "receive the goods" at the end)

5.5 Interrupt Mechanism5.5 Interrupt Mechanism

Interrupts are a very important mechanism in computer systems:Interrupts are a very important mechanism in computer systems:

1. After an I/O device completes an operation, it sends an interrupt request to the CPUAfter an I/O device completes an operation, it sends an interrupt request to the CPU
2. The CPU, currently executing an instruction, responds to the interrupt after completing the current instructionThe CPU, currently executing an instruction, responds to the interrupt after completing the current instruction
3. The CPU saves its current state and jumps to the interrupt handlerThe CPU saves its current state and jumps to the interrupt handler
4. After handling is complete, it restores the state and continues executionAfter handling is complete, it restores the state and continues execution

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6. CPU Performance Optimization: Pipeline Technology6. CPU Performance Optimization: Pipeline Technology

6.1 Instruction Pipeline6.1 Instruction Pipeline

Instruction pipelining is a parallel technique that maximizes CPU efficiency:Instruction pipelining is a parallel technique that maximizes CPU efficiency:

How Pipelining WorksHow Pipelining Works

CODE 📋 Salin📋 Copy

Sequential execution (5 instructions, 15 cycles): Instr 1: IF→ID→EX→MEM→WB Instr 2: IF→ID→EX→MEM→WB Instr 3: IF→ID→EX→MEM→WB ... Pipeline execution (5 instructions, 9 cycles): Instr 1: IF→ID→EX→MEM→WB Instr 2: IF→ID→EX→MEM→WB Instr 3: IF→ID→EX→MEM→WB ...

Ideally, CPI (cycles per instruction) for N instructions ≈ 1Ideally, CPI (cycles per instruction) for N instructions ≈ 1

6.2 Pipeline Hazards6.2 Pipeline Hazards

While pipelining improves performance, it also introduces hazard problems:While pipelining improves performance, it also introduces hazard problems:

Type	Cause	Solution
Structural hazard	Hardware resource conflict	Add hardware / stagger execution
Data hazard	Later instruction needs the result of an earlier one	Data forwarding / bubbles / scheduling
Control hazard	Branch instructions change execution flow	Delay slots / branch prediction

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7. Summary: The Computer Execution Model7. Summary: The Computer Execution Model

Let's connect the entire process using professional terminology:Let's connect the entire process using professional terminology:

> After a program starts, the operating system loads the executable file from disk into memory. The CPU's fetch unit (IF) reads instructions from memory into the instruction register (IR) via the address bus. The control unit decodes the instruction (ID), and after identifying the operation type, generates the corresponding control signals. The arithmetic unit (EX) performs arithmetic and logic operations. If memory access is needed, it accesses memory (MEM) via the data bus, and finally the result is written back (WB) to a register or memory. The entire process is driven by the clock, with micro-operation sequences generated by the control unit coordinating all components to work in an orderly manner.> After a program starts, the operating system loads the executable file from disk into memory. The CPU's fetch unit (IF) reads instructions from memory into the instruction register (IR) via the address bus. The control unit decodes the instruction (ID), and after identifying the operation type, generates the corresponding control signals. The arithmetic unit (EX) performs arithmetic and logic operations. If memory access is needed, it accesses memory (MEM) via the data bus, and finally the result is written back (WB) to a register or memory. The entire process is driven by the clock, with micro-operation sequences generated by the control unit coordinating all components to work in an orderly manner.

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Further ReadingFurther Reading

Topic	Recommended Resources
Computer Architecture	Computer Organization and Design: The Hardware/Software Interface - Patterson & Hennessy
CPU Microarchitecture	Computer Systems: A Programmer's Perspective - Bryant & O'Hallaron
Instruction Set Architecture	ARMv8 Architecture Manual, Intel x64 Manual
Cache Principles	Cache Coherence Protocol (MESI), Cache Write Policies
Operating Systems	Next chapter: "Operating Systems"

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Next StepsNext Steps

Now that you've mastered the professional knowledge of computer organization, you can continue learning:Now that you've mastered the professional knowledge of computer organization, you can continue learning:

• [Operating Systems](./operating-systems.md): Understand how programs run on an operating system, and how processes, threads, and memory management are implemented[Operating Systems](./operating-systems.md): Understand how programs run on an operating system, and how processes, threads, and memory management are implemented
• [Data Encoding, Storage, and Transmission](./data-encoding-storage.md): Deepen your understanding of how data is represented in computers[Data Encoding, Storage, and Transmission](./data-encoding-storage.md): Deepen your understanding of how data is represented in computers
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